In general, non-volatile memory devices are capable of storing data, even with power turned off. Non-volatile memory devices may be provided using flash memory cells with stacked gate structures. A flash memory cell with a stacked gate structure may provide non-volatile memory characteristics and allow data to be written and/or erased electrically. In addition, a flash memory cell with a stacked gate structure may allow a high degree of integration with a sequential stacked structure of a floating gate and a control gate electrode. As a result of these characteristics, a flash memory device using flash memory cells having the stacked gate structure have been adopted for use as storage media for portable electronic products and/or next generation storage media. A flash memory cell with a stacked gate structure will be discussed with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a conventional flash memory cell having a stacked gate structure. Referring to FIG. 1, a device isolation layer (not shown) may be provided on a predetermined region(s) of a semiconductor substrate 1 to define an active region(s). A control gate electrode 5 crosses over the active region. A floating gate 3 is provided between the control gate electrode 5 and the active region. A tunnel oxide layer 2 is provided between the floating gate 3 and the active region. The tunnel oxide layer 2 may be formed from a thermal oxide layer. A gate interlayer oxide layer 4 may be provided between the floating gate 3 and the control gate electrode 5. The gate interlayer oxide layer 4 may be formed from a silicon oxide layer deposited using chemical vapor deposition (CVD). Source/drain regions 6 may be provided in the active region on opposite sides of the control gate electrode 5.
The floating gate 3 is electrically isolated, and data stored in the flash memory cell may be either a “logic 1” or “logic 0” according to an electrical charge of the floating gate 3.
With a relatively high-integration of memory devices, a turn-on current of the flash memory cell may be reduced as the width of a channel region under the floating gate 3 is reduced. Accordingly, a sensing margin of the flash memory cell may be reduced, To maintain an acceptable sensing margin, an operation voltage may be increased. In addition, overlapped areas between the floating gate 3 and the control gate 5 may be reduced, and a coupling ratio of the flash memory cell may thus be reduced. For these reasons, smaller flash memory cells may require higher operating voltages, and power dissipation may thus be increased. Moreover, an interface between the tunnel oxide layer 2 and the active region may be damaged by higher operating voltages, and reliability of the flash memory cell may be reduced.